\section{Introduction} \label{sec:introduction}

With the technology scaling, the number of cores and the total die
area in CMP increase. Consequently, the yield of functional cores is
reduced, resulting higher cost. 3D may provide cost efficiency with
smaller stacking die size when the corresponding 2D die has large
area(xiangyu's paper). To further improve performance/cost, the
interconnect between cores and caches can be designed for the
reconfigure and fault-tolerant purpose so that when some cores are
not functional their caches can be used by any other core or
neighboring cores (different complexity of interconnect). (expand
this section later: CMP, yield, 3d technology, communication node,
and cost)

Technology from 130nm-90nm-65nm-45nm, the number of cores can be
from 4 cores-8 cores-16 cores-32 cores-64 cores, cache size may also
change. The number of tiers in 3D is from 2-3-4 layers. focus on one
technology first.

Contributions for the proposed paper:

1. Mapping compute, communication and storage (including cache)
functions to 3D stacking, but extracting communication functions
from conventional cache/memory and logic layers in 3D.

2. Enhance communication layer to a "service" layer for cost
reduction (reduced hop counts), flexibility (multiple alternative
connection points to the storage and compute layers) and reliability
(redundant wiring within or across topology layers) via
"hierarchical" network topology - not necessary "hybrid", i.e.,
different topology as in Das' HPCA'09 paper.

3. Improvement over Xiangyu's (Andrew Kahng's) model in addition to
gate/area count and technology nodes calculation, by distinguishing
cost models between the three functional layers, addressing
(product) volume factor of each layer, addressing (production) time
factor of each layer, etc (different technology for memory/core,
various storage size under the same area constraint, evaluate cost
and performance)

1. the cost model for 3D with technology scaling, die area, number
of layers, number of TSVs.

2. interconnect layer: enable cache reuse when the cores are not
working.(other purpose: increase core voltage when it requires
higher voltage to work, reliability service...) the area, power,
performance evaluation of the interconnect layer. different
topologies: shared bus/crossbar, mesh/ring architecture.
fully-connected/hierarchical

3. the interconnect layer can be integrated with existing core layer
and cache layer or can be separately a single layer depending on the
number of cores, number of layers, the area of the logic and the
cost.

4. performan/cost evaluation: depending on how many cores are
working, what kind of interconnect is used.

5. provides the methodology to help design choices on different
layers, interconnect structure, improve yield of CMP in 3D...



Then new title can be: When 4C meets 3D - Cost-driven design of
Compute, Communication and Composition (storage) layers in 3D
stacked chips.
